(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming solder bumps for flip-chip applications.
(2) Description of the Prior Art
A continued decrease in semiconductor device feature size, a decrease that is driven by the dual requirements of improved device performance and reduced device manufacturing cost, has over the years resulted in placing increased emphasis on device packaging. This trend has further, due to a significant increase in semiconductor device density, placed increased emphasis on device or package I/O capabilities. The metal connections, which connect the Integrated Circuit to other circuit or system components, have therefore become of relative more importance and potentially have, with the further miniaturization of the IC, an increasingly negative impact on the circuit performance. If the parasitic capacitance and resistance of the metal interconnections increases, the chip performance can be degraded significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
One of the approaches that has been taken to solve these packaging problems is to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines. Another approach to solve problems of I/O capability has been to design chips and chip packaging methods that offer dependable methods of increased interconnecting of chips at a reasonable manufacturing cost. This has led to the development of Flip Chip Packages.
Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads on the chips and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest paths. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to more sophisticated substrates that accommodate several chips to form larger functional units.
The flip-chip technique, using an area I/O array, has the advantage of achieving the highest density of interconnection to the device combined with a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and Coefficient of Thermal Expansion (CTE) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder-lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations.
The packaging substrate is generally used for Ball Grid Array (BGA) packages but can also be used for Land Grid Array (LGA) and Pin Grid Array (PGA) packages.
Prior Art substrate packaging uses ceramic and plastic flip chip packaging. Ceramic substrate packaging is expensive and has proven to limit the performance of the overall package. Recent years has seen the emergence of plastic substrate flip chip packaging, this type of packaging has become the main stream design and is frequently used in high volume flip chip package fabrication. The plastic substrate flip chip package performs satisfactorily when used for low-density flip chip Integrated Circuits (IC's). If the number of pins emanating from the IC is high, that is in excess of 350 pins, or if the number of pins coming from the IC is less than 350 but the required overall package size is small (resulting in a solder ball pitch of less than 1.27 um.), the plastic flip chip structure becomes complicated and expensive. This can be traced to the multi-layer structure used to create the plastic flip chip package. This multi-layer structure results in a line density within the package of typically 2-3 mil or 50 u-75 u range. This line density is not sufficiently high for realizing the fan out from the chip I/O to the solder balls on the package within a single layer, leading to the multi-layer approach. The multi-layer approach brings with it the use of relatively thick (50 u-75 u) dielectric layers, these layers have a Coefficient of Thermal Expansion (CTE) that is considerably higher than the CTE of the laminate board on which the plastic flip chip package is mounted. To counteract this difference in CTE's the overall package must be (thermally and mechanically) balanced resulting in the use of additional material and processing steps to apply these materials, increasing the cost of the BGA package and creating a yield detractor.
Other Prior Art applications use thin film interconnect layers for chip or wire bond packaging substrates. These applications start with a laminate substrate onto which the thin film layers are deposited. For these applications, the laminate substrate is used as a base carrier substrate and provides the mechanical support. Plated Through Holes (PTH) are mechanically drilled through the laminate substrate and are used to establish connections to the backside of the substrate for solder ball attach and electrical contacts. By using thin films, high wire density and very thin dielectric layers can be realized. This approach also does not require the counter-balancing of thick layers of dielectric in order to establish dimensional stability. A disadvantage of the laminate substrate is that the process of mechanically drilling holes through the laminate substrate is time-consuming, adding cost to the process. Further, the planarity of the laminate substrate does not meet planarity requirements for the deposition of thin films. Good planarity for the surface of the laminate substrate is established by depositing dielectrics and metal layers on the initial surface of the laminate structure, steps that again add to the processing cost of the flip chip structure. Since the laminate substrate is composed using organic materials, the substrate is also not dimensionally stable resulting in warpage and dimensional variations during high temperature processing and wet chemical interactions. This results in additional processing complications and costs.
The packaging of a flip chip to a printed circuit board consists of attaching the flip chip to this board or to any other matching substrate. A flip chip is a semiconductor chip that has a pattern or array of terminals spaced around the active surface of the flip chip, the flip chip is mounted face (active surface) down onto a substrate. Electrical connectors that are provided on the active surface of the flip chip can consist of Ball Grid Arrays (BGA's) and Pin Grid Arrays (PGA's). With the BGA, an array of minute solder balls is disposed on the surface of the flip chip for attachment to the surface of the substrate. For PGA's, an array of small pins extends essentially perpendicularly from the active surface of the flip chip, such that the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment. An extension of the BGA concept is the Slightly Larger than Integrated Circuit Carrier (SLICC) arrangement which is characterized by a smaller solder ball pitch and a smaller solder ball diameter than the BGA. It is clear that the solder or other conductive ball or pin arrangements of the flip chip must be a mirror image of the connecting bond pads on the printed circuit board so that precise connection can be made. The flip chip is bonded to the printed circuit board by refluxing the solder balls or pins (for the PGA) of the flip chip. The solder balls may also be replaced with a conductive polymer.
Flip chips are typically hermetically sealed to the substrate by using glob top and underfill materials between the flip chip and the substrate. Not all flip chip packages use chip back surface protection (glob top) leaving the chip exposed to environmental damage. The underfill encapsulant generally enhances the attachment of the semiconductor die to the substrate while providing environmental protection to the chip. The application of the underfill in particular must be carefully monitored in order to avoid problems of void creation, contaminant penetration and overfill that may cover the edges of the chip or that can spread to adjacent areas of the board that do not require fill. A variety of polymers can be used as underfill encapsulants, including thermosetting molding compounds such as silicones, epoxies, polyamides and parylenes. A glob of encapsulant material is generally applied to the COB assembly to surround the semiconductor chip and the substrate. Organic materials that are used in the glob top encapsulation are generally selected for their low moisture permeability and low thermal coefficient of expansion to avoid moisture or mechanical stress. It is critical that all encapsulation methods and materials are aimed at maximizing the heat transfer between the chip and the substrate and other environmental media thereby improving heat dissipation characteristics of the overall package.
Conventional methods that are used to create metal bumps on the surface of a wafer are highlighted in FIGS. 1a through 1e. During this process it is important to carefully consider the eutectic characteristics of the materials that are use. Eutectic is defined as a material formed of an alloy or solution having its components in such proportions that the melting point is the lowest possible with such components. The eutectic properties of a material also refer to the characteristic microstructure that results when the material solidifies. In short: the materials that are used for these processes must be such that reflow of the solder balls is possible without significantly affecting the quality of the electrical interconnect that is established by the reflow.
FIG. 1a shows an electrical pad or point of interconnect 12 that has been created in a semiconductor surface 10, typically the surface of a substrate. A layer 14 of dielectric material is deposited over the surface of the substrate thereby including the surface of the pad 12. An opening 18 is created in layer 14; this opening aligns with the pad 12. A layer 16 of metal, typically referred to as the Under Bump Metal (UBM) and also referred to as the barrier layer, is blanket deposited over the layer 14 thereby including the inside walls and bottom of the opening 18.
FIG. 1b shows how the contact opening is prepared for the deposition of the bump metal. A layer 20 of photoresist is deposited and patterned, this pattern aligns with opening 18.
FIG. 1c shows the deposition of the metal for the bump on the surface of the substrate. This metal 22 can for instance be copper or nickel. The deposition is an electrochemical deposition whereby the layer 16 of UBM is connected to one of the electroplates.
FIG. 1d shows the cross section after the removal of the layer of photoresist (layer 20, FIG. 1c).
FIG. 1e shows how the bump is made to further protrude from the surface of the wafer by performing an etch whereby the layer 16 of UBM and the dielectric/passivation layer 14 surrounding plug 22 are removed.
Another Prior Art method of forming metal bumps (not shown) is a process whereby a metal contact pad is created in a semiconductor surface, a layer of dielectric material is deposited and patterned whereby-the openings created in this layer align with the metal pad. A barrier layer is deposited inside the created opening, a layer of photoresist is deposited and patterned over the layer of dielectric whereby the openings created in the layer of photoresist again align with the metal pad. The process that has been described up to this point results in a cross section that is identical to the cross section shown in FIG. 1c. The metal plug is now formed by methods of rf sputtering after which the various layers can be removed from the region surrounding the created metal plug leaving the metal plug protruding from the surface and aligned with the metal pad. The disadvantage of this method is the layer of photoresist that must be applied as part of the procedure must be 20 .mu.m thick due to limitations imposed by the rf sputtering process (providing adequate protection against penetration of the sputtered metal). It is well know in the art that it is difficult to form photoresist accurately when applied very thick. Multiple steps can be used to increase the thickness of the layer of photoresist; this however increases the cost of the process. This limits the design freedom that is required in designing metal plugs because a photoresist coating of this thickness does not allow the creation of solder bumps with a small distance (pitch) between adjacent bumps.
Yet another Prior Art method (not shown) depends on methods of etching to create the profile of the metal plug. This method suffers from the disadvantage that copper, used for the metal plug, is difficult to etch while again a layer of photoresist must be-used that is 20 .mu.m thick, leading to the same design limitations as already highlighted.
Yet another Prior Art method applies Physical Vapor Deposition (PVD) through a metal mask. This method is very slow since the deposition rate using this technique is about 500 Angstrom per minute. This as opposed to a metal deposition rate when using Electrical Chemical Deposition (ECD) technology of 3500 Angstrom per minute. In view of the fact that a typically metal bump is required to have an extension or thickness of about 5 to 20 .mu.m, it can be appreciated that the approach of using either PVD or ECD technology is unacceptably slow in the deposition of the plug metal. In addition, the indicated method suffers from poor mask alignments and from poor pattern definition and resolution.
The invention addresses the above-indicated problems that are encountered during conventional creation of metal bumps. The invention does not use the method of electrochemical deposition FIGS. 1a through 1e or the method of rf sputtering or the method of etching or the method of PVD/ECD that have previously been highlighted under the Prior Art approaches in creating metal bumps.